2015/08/17

Introduction to Open Schematic Capture

Scope

Present day mixed analog/digital integrated circuits (IC) are usually implemented in a CMOS technology having both high voltage ( usually 5V or 3.2V ) and low voltage ( 2.4V or below ) devices. They have a reasonably large section of digital circuitry implemented with the low voltage gates (gates, flip flops, tri state buffers, etc.) often supplied by the IC fab or by a third party. Digital design entry is often done in VHDL or Verilog, the 2 most popular hardware definition languages (HDL). The analog part of the IC consists of analog circuits and high voltage digital gates that can interface directly with the analog circuits. Analog design entry is usually done with a conventional schematic entry tool. Digital level shift buffers are placed between the low voltage digital and analog halves of the circuit.

Design is done by a team of engineers using or developing multiple libraries of cells. Some libraries are project specific, some are company wide, and some come from third parties.

Open Schematic Capture (OSC) is intended to support this environment. OSC provides a data base structure designed for the easy integration of circuit design, simulation, and layout data as well as the project specific process library.

OSC is written in the Java programming language, which makes it portable across all operating systems supporting the java language.

Schematic Entry, Net Listing, and Simulation

OSC supports schematic entry, net listing, layout, and, to a degree, simulation.

Handling Digital

Handling digital is a challenge. Doing design entry in HDL, as is done in most commercial tools, requires a program to take the HDL code and synthesize real gates. To the best of my knowledge, no such program exists in the open source world. So, in OSC, digital design entry is done with schematics. OSC tries to optimize this process by supporting "for" and "if" frames to give the schematic entry tool something of a graphical programming feel. This seems to work fairly well and may actually have some advantages over HDL.

There are, however, a number of open source HDL simulators, and generating HDL code from schematics is fairly easy. Since VHDL seems to cover the needs of a full chip simulation better than Verilog, OSC uses VHDL as the HDL of choice and supports the generation of VHDL net lists from its schematics for use in digital simulation.

Rev. 0.24 of OSC is starting an attempt to better integrate VHDL. It has a VHDL parser, a VHDL to Java simulation code generator, and a simulator that, at this point, support only a subset of the VHDL language.

Simulation

For an open source schematic entry tool to make sense, there needs to be open source simulators to check the correctness of the design. The OSC schematic entry tool is simulator agnostic, but the libraries and net listers have been "tuned" to the simulation tools listed below.

There tend to be 4 levels of simulation, analog, mixed, digital, and system.

Analog

OSC supports net listing in Spice syntax. Spice syntax is very generic and should be compatible with most analog simulators. NGSpice (ngspice.sourceforge.net), an independent project which has its roots in the original Berkeley Spice, is used for the enclosed example project. The OSC data viewer can display NGSpice transient analysis output saved as "raw" data in binary format.

Mixed

Analog simulations are slow. If there is a significant amount of digital included in the simulation, the simulation can be sped up by treating the digital as event driven logic rather than analog circuits. NGSpice supports this with an extension added from a project called XSpice. The digital gates require a slight tweak on the Spice syntax, which the OSC net lister supports.

Digital

As mentioned, OSC also supports net listing in VHDL syntax for full digital simulations. Digital cells are net listed directly from the schematics.

Since VHDL supports "real" numbers and is fairly versatile it is possible to write VHDL models of analog cells that are good enough for top level simulations. This allows for running meaningful full chip simulations in something less than an infinite amount of time. OSC will generate a VHDL template for a analog circuit and place it in <circuit_path>/vhdl.view/model.vhd. This is only intended to be used as a digital simulation model of an analog circuit and will be incorporated into the VHDL netlist. The template must be hand edited to fill in the code for the model.

Simulations for the example project were done in GHDL (ghdl.free.fr), another independent project, but VHDL is an IEEE standard and so the net lists should work on any VHDL digital simulator. The GHDL output seems to be best viewed on gtkwave (gtkwave.sourceforge.net).

As mentioned, experimenting has begun on a native VHDL simulator.

System

System level simulations are high level simulations, where the chip being designed is one of many components that must work together to form the system. OSC includes a system level simulator which uses Spice format that can be generated from the net lister. The simulator is an event driven, fixed discrete time simulator, much like a digital simulator. However, it is targeted toward analog simulations. System component models are written as Java source files, which are compiled into class code files at the beginning of each simulation. This allows for complex models to be written to describe the environment in which the chip works or for high level models of the chip itself. The output data can be viewed with the OSC data viewer.

Because Java source code must be compiled into class files, the simulator must have access to a Java compiler (javac). The Java compiler may not be included in minimal Java installations, but is freely available.

In addition to net listing, OSC also structures its data base to allow for the storage of model files and simulation control scripts.

Net List Control

In order to support the simulations and layout verses schematic (lvs) checks listed above, OCS must be able to adjust its net list output. It does this by using "if" frames. In a schematic, if a section of circuitry is surrounded by an "if" frame, that circuitry is net listed only if the "if" statement evaluates to "true" using the net list control parameters fed into it for the particular net list being run.

Layout

Originally, OSC was not intended to support layout. However, Magic (opencircuitdesign.com/magic) is a IC layout program that was developed at UC Berkeley in the 80's, is still widely used and its sorce code, written in C, is available. So, Magic is being translated into Java and incorporated into OSC. This is a slow process and right now the layout tool is reasonably functional, still with bugs and holes.

Example Project

As mentioned, an example of a mixed mode IC has been included in the data base. It is intended to check the schematic entry and net lister tools and to provide an example of how the tools were intended to be used. It is not yet fully implemented and simulated. Therefore, it will have implementation short cuts and empty functional blocks. Also, I am sure there are a number of design errors. The design will eventually be completed, as time permits.

Tools are best tied together ( in my humble opinion ) by shell scripts. Linux Bash scripts and some MS Windows scripts can be found in <install_path>/open_sch_capt_data/osc_macros. Bash scripts that run simulations can also be found in <circuit_path>/vhdl.view, <circuit_path>/system.view, and <circuit_path>/spice.view directories scattered through out the example project. MS Windows versions of these scripts should be fairly easy to generate.

Layout of the example is in an early stage and is using the C version of the Magic layout program.

Complete Design Flow

OSC, by itself, is a cross platform tool, since it is written in Java. However, as you add other tools and the shell scripts to tie them together, a complete design flow becomes very platform specific. It seems that Linux is the best platform choice, since the best open source tools seem to be written for it. The Fedora Linux distribution, in particular, provides pre-compiled versions of the simulation and layout programs mentioned above in its repositories.

Documentation

Documentation is somewhere between poor and non-existent. There is limited information in the <install_path>/osc_info_files directory. Beyond that, the example project is your best bet on figuring out how stuff works.


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